1. Field of the Invention
The present invention relates to nonvolatile memory (NVM) cells, and in particular to programming methods for NVM cells.
2. Description of the Related Art
Prior programming methods for nonvolatile memory cells based upon P-channel insulated gate field effect transistors (P-IGFETs), e.g., P-type metal oxide semiconductor field effect transistors (P-MOSFETs), as applied to conventional stacked gate cells, have used either pulses of negative voltage applied to the drain electrode with the shorted source and bulk regions grounded, or pulses of positive voltage applied to the shorted source and bulk regions while the drain region is grounded. Such methods can provide reasonably good programming, provided that the coupling ratio between the control electrode and the floating gate as well as the erasing conditions remain consistent. However, variances in either or both of these factors can introduce significant variances in programming results.